BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning Acceleration

Most of weights in deep learning models are small, thus they show high bit sparsity in MSBs. Based on this observation, we propose a bit-serial processing architecture (BS2) that exploits such bit sparsity to maximize computing efficiency. In this architecture, a bit feed front-end (BFFE) logic selects only effectual operands that will be fed into a bit-serial adder-tree. We also introduce an offline weight permutation algorithm to avoid conflicts in the BFFE. Evaluation results show that our design outperforms the previous bit-serial architecture in terms of performance and energy efficiency.