Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects

The long-term reliability of Static Random Access Memory (SRAM) is crucial for safety-critical applications, such as those in the automotive industry. In the front-end-of-line (FEoL), the transistor elements are susceptible to negative bias temperature instability (NBTI), while in the back-end-of-line (BEoL) the interconnects are susceptible to electromigration (EM), especially in scaled technology nodes. To meet safety-critical standards, it is essential to investigate the combined aging mechanisms within the SRAM array and to develop effective testing methodologies during the operational lifetime of the system. Such methodologies are also crucial for enabling the early detection of in-field failures. In this paper, a precise aging model is presented that extends the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model and includes physical modeling for EM. This approach provides insights into the combined effects of NBTI and EM on the degradation of SRAM writability, considering the entire SRAM subarray, including the bit-cell array and peripheral circuits in Fin Field-Effect Transistors (FinFET) technology.