FPGA Design of a Masked AES Circuit with PPRM-based S-Box

FPGA devices are at present widely used in IoT applications. To ensure the security of IoT communication, data must be encrypted using algorithms such as AES. However, since IoT devices are deployed in the field, there is a risk of side-channel attacks even if communication is encrypted. In this work, an AES circuit resistant to power side-channel attacks is designed for FPGA, implementing a masking countermeasure. Through experiments, we evaluate the resilience against side-channel attacks as well as the hardware resource and power overheads.