From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel

In the rapidly evolving landscape of System-on-Chip (SoC) design, Intel has faced unique Design-for-Testability (DFT) challenges that commercially available Electronic Design Automation (EDA) solutions could not address. This paper explores Intel’s transition from a proprietary hybrid test and debug integration solution to a new, innovative DFT integration solution based on industry standards and Siemens’ Tessent Platform. The new solution integrates both proprietary and vendor-provided DFT logic, addressing the shortcomings of the legacy flow. This paper details the challenges of the legacy solution, the development of the new solution, and its impact on future SoC design and testing at Intel.