Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed

Recent technological developments, such as artificial intelligence, require memory enhancements for better data transfer and computation capabilities to improve performance. This paper presents a 16-Kb 6T SRAM supporting wide parallel data access to improve computation efficiency. The proposed SRAM supports two operation modes with the aid of the internal digital command controller (IDC): a conventional data access (CA) mode and a wide parallel data access (WPA) mode. In the CA mode, the data write and read operations are performed based on the specific row and column addresses. However, the WPA mode activates all columns in the target row to access large amounts of data in parallel; thus, this mode can be used in various compute-in-memory applications. The prototype chip was fabricated in a 28-nm CMOS process. Activating all columns results in data access speeds that are 8 times faster than the CA mode.