High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security Applications

With its simple and highly flexible instruction set, the RISC-V architecture is considered the optimal solution for security applications requiring high-performance and low-power cryptographic hardware. However, existing RISC-V processors for cryptography still suffer from low performance. To solve this problem, this paper proposes a RISC-V-based cryptographic coprocessor referred to as "Co-RISCV" to achieve high speed and hardware efficiency. The real-time performance results of our Co-RISCV at an actual System-on-Chip (SoC) level on the Xilinx ZCU102 FPGA platform demonstrate that the Co-RISCV is better from 1.2 to 14.3 times than modern CPUs in power efficiency. Compared with related works, the Co-RISCV also shows an improvement of 1.13 to 3.31 times in terms of throughput measured in cycles per byte.