Power-Aware Test Scheduling for Memory BIST

An increasing number of embedded memory instances, despite lowering the power supply voltage and technology node size, leads to higher power dissipation during the memory test phase when manufacturing a System-on-Chip (SoC). Commonly used manual memory test scheduling techniques need to be replaced with more systematic approaches. The objective is to minimize the test time through concurrent memory testing, resulting in maximization of the dissipated power, but in the way the given power budget is not exceeded. The paper comprises two topics. Firstly, it presents a toolchain aimed at a thorough monitoring of the power dispersed by memory instances and associated Memory Built-In Self-Test (MBIST) instruments. Secondly, several algorithms are proposed that optimize the memory test scheduling for a commercial Design-for-Test (DFT) tool.