3T1R Memristor Crossbar Architecture for Diverse Logic Implementation

With the recognition of the Von Neumann architecture’s limitations, in-memory computing has emerged as a promising alternative computing paradigm, prominently exemplified by the Logic-in-Memory (LiM) architecture that exploits memristors. While the memristor-aided logic (MAGIC) is proposed to present several logic operations only with memristors, it can only execute NOR and INV operations in parallel on the memristor crossbar. This paper proposes a novel 3T1R memristor crossbar structure capable of configuring series circuits and executing various gate operations. Furthermore, we introduce the optimization scheme for a full adder within our structure, in terms of latency and area. Experimental results verify that the gate operations work correctly in our 3T1R structure, and that the full adder implemented in the 3T1R structure reduces latency and area by 33.8% and 50.2%, respectively.

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Published
2024-08-19
DOI
https://doi.org/10.1109/isocc62682.2024.10762169
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.00

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article

3T1R Memristor Crossbar Architecture for Diverse Logic Implementation

Heechun Park, Ikkyum Kim
Advanced Memory and Neural Computing
article

3T1R Memristor Crossbar Architecture for Diverse Logic Implementation

Heechun Park, Ikkyum Kim
article en

Abstract

With the recognition of the Von Neumann architecture’s limitations, in-memory computing has emerged as a promising alternative computing paradigm, prominently exemplified by the Logic-in-Memory (LiM) architecture that exploits memristors. While the memristor-aided logic (MAGIC) is proposed to present several logic operations only with memristors, it can only execute NOR and INV operations in parallel on the memristor crossbar. This paper proposes a novel 3T1R memristor crossbar structure capable of configuring series circuits and executing various gate operations. Furthermore, we introduce the optimization scheme for a full adder within our structure, in terms of latency and area. Experimental results verify that the gate operations work correctly in our 3T1R structure, and that the full adder implemented in the 3T1R structure reduces latency and area by 33.8% and 50.2%, respectively.

Ulsan National Institute of Science and Technology (KR)
National Research Foundation
Affordable and clean energy
Openalex Percentile: Top 81%
Advanced Memory and Neural Computing
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