Opportunities and Challenges of DRAM-based Computing-in-Memory for AI Accelerator

Recently, computing-in-memory (CIM) has been attracting attention as an implementation method that can improve AI accelerators' energy efficiency and operation density. By integrating computing logic inside a memory cell array, CIM can consume less area and energy. Research on static random access memory (SRAM)-based implementations has grown most rapidly in the past few years. The rationale behind this trend is rooted in SRAM's stable storage with its cross-coupled storage node that can apply various computational methods. However, SRAM-based implementation has density limitations due to the requirement of 6 transistors per 1-bit storage. Therefore, dynamic random access memory (DRAM)-based CIM is proposed to overcome this problem. DRAM-based CIM uses only one to four transistors per cell, which creates new challenges such as leakage impact on computation and destructive read. Since DRAM cells store values on capacitors, the calculation results may be affected if the values are degraded due to leakage. Additionally, if a gain cell that requires an additional transistor is not used, a destructive read occurs and must be refreshed for each operation. We would like to review circuit, architecture, and algorithm-level solutions to solve these challenges In the latest DRAM-CIM research and discuss future directions of DRAM-CIM.