SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits

Due to Moore’s law limitations, SiP became popular in recent years among industries to increase functionality density, by integrating multiple chiplets on a shared interposer substrate. To reduce the time-to-market, SiP designers need to outsource their SiPs to untrusted testing facilities, relinquishing control during testing. However, it leads to over-production and counterfeit threats. In this paper, we propose a novel framework SECT-HI aimed at establishing a secure testing environment for SiPs by granting control of the test procedure to the SiP designers. To mitigate the risks of overproduction and distribution of out-of-spec, faulty SiPs, the SiP’s functionality remains locked until the SiP designer provides the correct key. Additionally, the scan chain responses are also encrypted to prevent unauthorized access from test facilities creating a golden response database. Further, a watermark is added to deter counterfeits. Extensive simulation results demonstrate that the SECT-HI framework introduces an area and timing overhead of only 1.1-3.4% and 280ms respectively while adhering to the packaging criteria for 2.5D/3D SiPs.