Design of a 3D-IC based AI-Vision SoC

This paper proposes a 3D-IC design for AI-Vision SoCs to address the limitations of performance and functionality inherent in using traditional 2D-ICs within a limited form factor. We defined criteria for subsystem partitioning focused on performance, power, and area (PPA) and implemented a 3D-IC with an efficient subsystem top and bottom die layout. The implementation results show a significant reduction in die area to approximately 59.7% of a comparable 2D-IC, including a 3D-I/O overhead of 0.285 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>