Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors

Although highly energy efficient, adiabatic and reversible systems suffer from performance drawbacks inherent to the physical operations that make them so efficient. Superscalar processors provide high performance through out-of-order speculative work of which an effective branch predictor is a key component in those performance gains. In the context of reversibility, a branch predictor is a design focal point because any fully reversible system must also be able to predict branch outcomes when in reverse mode. Taking advantage of Temporal Streaming techniques, this paper introduces several reversible branch predictor implementations which enable reversible and out-of-order instruction execution. These first-of-their-kind designs allow for a superscalar architecture that would maintain both a high level of performance and a high level of energy efficiency with the ability to un-compute obsolete data stored in memory. Testing our designs using the SimpleScalar out-of-order simulator, we estimate possible additional savings of 24 fJ per MB of data recovered at room temperature and at reverse prediction rates 2.27% higher than the forward. This work opens new avenues for designing and developing what we are calling Fully Adiabatic, Reversible, and Superscalar (FARS) Processor Architectures and is the first of many adaptations of conventional superscalar components to a reversible system.