A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications
Although custom designs for AI/ML workloads on resource-constrained devices are capable of high energy efficiency, they are usually tailored for a single task or a narrow range of applications. Coarse-grained reconfigurable arrays (CGRAs) can bridge this gap by using software-defined computing engine to offer both energy efficiency and flexibility across wide range of workloads. This work presents a versatile CGRA design with 17 integer and logic instructions, multi-hop data transfers and hardware customized idle-state power saving op-code. The proposed CGRA was fabricated in the 40nm technology node and delivers a peak efficiency of 360 GOPS/W, which is 1.2× to 4.6× higher than the state-of-the-art.
Authors
- Yi Sheng Chong (ORCID: https://orcid.org/0000-0003-4136-6570)
- Thilini Kaushalya Bandara (ORCID: https://orcid.org/0000-0003-3413-136X)
- Vishnu P. Nambiar (ORCID: https://orcid.org/0000-0001-5570-5911)
- Tulika Mitra (ORCID: https://orcid.org/0000-0003-4136-4188)
- Li-Shiuan Peh (ORCID: https://orcid.org/0000-0001-9010-6519)
- Rohan Juneja (ORCID: https://orcid.org/0000-0002-6015-1084)
- Dhananjaya Wijerathne (ORCID: https://orcid.org/0000-0003-3181-2514)
- Zhi Li (ORCID: https://orcid.org/0000-0001-9813-4979)
- Anh Tuan (ORCID: https://orcid.org/0000-0002-8320-6818)
Institutions
- Agency for Science, Technology and Research (SG)
- National University of Singapore (SG)
- Institute of Microelectronics (SG)
Publication Details
- Published
- 2024-08-19
- DOI
- https://doi.org/10.1109/isocc62682.2024.10762131
- Citations
- 3
- Primary Topic
- Interconnection Networks and Systems
- Type
- article
- Field-Weighted Citation Impact
- 1.05
Funders
- National Research Foundation