A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process

Driver designs for power transistors need to consider performance and efficiency simultaneously. This work demonstrated an active gate driver (AGD) that drives the power transistor at multiple voltage levels using a multi-level power gating logic. A power gating mechanism reduces AGD power consumption. AGD’s Four-Level Balance Control Circuit ensures that all power MOS devices in the Output Stage’s buffer arrays are used. The AGD was implemented using TSMC 180-nm High-Voltage BCD (Bipolar-CMOS-DMOS) technology. AGD design capability was proven using all-PVT-corner post-layout simulations with C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">load</inf> = 2 nF and PWM frequency = 500 kHz. The static and dynamic power dissipation averages 167 mW. Finally, power gating reduces power by 122 mW, according to two cycles with and without it.