Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

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Publication Details

Published
2024-11-03
DOI
https://doi.org/10.1109/itc51657.2024.00068
Citations
2
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.42
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article

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard

Vidya Neerkundar, Ankita Patidar, Jonathan Gaudet, Frank J. Lee et al.
2 citations
Integrated Circuits and Semiconductor Failure Analysis
0.42
article

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard

Vidya Neerkundar, Ankita Patidar, Jonathan Gaudet, Frank J. Lee, Martin Keim, Sandeep Goel, Anshuman Chandra, Quoc Phan, Moiz Khan, Naim Lemar
article en
2 citations

Abstract

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

Taiwan Semiconductor Manufacturing Company (United States) (US), Taiwan Semiconductor Manufacturing Company (Taiwan) (TW), Siemens (United States) (US), Siemens Healthcare (United States) (US)
Openalex Percentile: Top 36%
Integrated Circuits and Semiconductor Failure Analysis
0.42
DOISourceOpenAlex
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Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard — Vidya Neerkundar, Ankita Patidar, et al. · (2024) | TGRS Research Map | TGRS