Estimation And Analysis of Power Consumption & Gate Delay of Product of Sum Function Based Digital Integrated Circuit

This work represents design and simulation of a CMOS digital VLSI circuit based on a Product of Sum (POS) expression using both Static and Dynamic CMOS design techniques. The proposed circuits have been designed and simulated at 180nm and 150nm CMOS technology nodes. The circuit’s functionality has been verified using of the T-SPICE tools. Gate delay, power consumption & power delay product (PDP) have been estimated to compare the impact of different design techniques. The variation of supply voltage from 0.6 V to 1.5 V has been considered to represent power delay analysis. The T-SPICE simulation results depicts that the optimum values of PDPs for Static CMOS circuit are 7.364aJ and 0.374aJ for 180nm and 150nm technology node respectively at VDD value 1V. The dynamic CMOS circuit offer lower optimum values of PDPs as 1.773aJ and 0.092aJ for 180nm and 150nm technology node respectively at VDD values 1.1V and 0.6V. Thus, this work may be useful for digital VLSI designer for the power delay analysis of VLSI circuits.