MHC : Multi-flit HBM Crossbar with Enhancing Performance and Resource Utilization

The bottleneck problem arises from the internal crossbar architecture within the HBM. Challenges related to the internal crossbar’s bandwidth in HBM primarily revolve around efficiently utilizing the memory’s considerable bandwidth on Field-Programmable Gate Array (FPGA) platforms. To tackle this issue, we propose the Multi-flit HBM Crossbar(MHC), which offers customized interconnections tailored for FPGA HBM boards, targeting high performance. The crossbar stage is designed using the Butterfly-Fat-Tree(BFT) structure, with multi-flit data format adoption. The effectiveness of MHC has been demonstrated through its application on the Xilinx Alveo U280 board. We have enhanced bandwidth across diverse addressing policies and noted that employing multi-flit leads to notable band-width improvements, especially with increasing burst lengths.