A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-Computing

This paper presents a software-hardware (SW-HW) co-optimization approach for DRAM in-memory computing, significantly reducing sense amplifier read power in 2T1C cell systems. By transitioning from 2's complement to signed magnitude representation, data '0' prevalence increased from 52% to 73%, achieving a 13% reduction in read power. A novel sense amplifier design incorporating a variable reference voltage contributed a further 15% power reduction. This co-optimization strategy resulted in a total read power decrease of 26% compared to the baseline, demonstrating substantial improvements in energy efficiency for memory-intensive computing environments.