A Fast-Lock All-Digital PLL with a TDC-based FLL

This paper presents a fast-lock all-digital phase-locked loop (PLL) for double-data rate (DDR) interface and zero-delay buffer applications. The proposed PLL utilizes a new time-to-digital converter (TDC)-based frequency-locked loop (FLL) to achieve a fast lock time. Implemented in a 40-nm 1.1V CMOS process, the proposed PLL achieves an operating frequency range of 1.5–3.2 GHz. It achieves a frequency lock time of approximately 100 ns and a phase lock of 310 ns or less. The simulated RMS jitter is 0.87 ps at 2.7 GHz. It occupies a core area of only 0.0345 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes a power of 6.2 mW at 2.7 GHz.