A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). There are multiple techniques for efficient use of scan bandwidth and its impact on the overall test cost and test quality. We have also architected various debug techniques for silicon bring-up. This scan architecture was designed for highest throughput to test multiple dies in parallel with lowest test power and best diagnosability.
Authors
- Shantanu Sarangi
- Kaushik Narayanun
- Mahmut Yilmaz (ORCID: https://orcid.org/0000-0002-4522-7028)
- Vishal Agarwal (ORCID: https://orcid.org/0009-0005-1428-0124)
- Kunal Jain Mangilal
Institutions
- Nvidia (United States) (US)
Publication Details
- Published
- 2024-11-03
- DOI
- https://doi.org/10.1109/itc51657.2024.00062
- Citations
- 1
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.21