A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS

Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). There are multiple techniques for efficient use of scan bandwidth and its impact on the overall test cost and test quality. We have also architected various debug techniques for silicon bring-up. This scan architecture was designed for highest throughput to test multiple dies in parallel with lowest test power and best diagnosability.

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Published
2024-11-03
DOI
https://doi.org/10.1109/itc51657.2024.00062
Citations
1
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.21
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A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS

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Integrated Circuits and Semiconductor Failure Analysis
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article

A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS

Shantanu Sarangi, Kaushik Narayanun, Mahmut Yilmaz, Vishal Agarwal, Kunal Jain Mangilal
article en
1 citations

Abstract

Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). There are multiple techniques for efficient use of scan bandwidth and its impact on the overall test cost and test quality. We have also architected various debug techniques for silicon bring-up. This scan architecture was designed for highest throughput to test multiple dies in parallel with lowest test power and best diagnosability.

Nvidia (United States) (US)
Openalex Percentile: Top 46%
Integrated Circuits and Semiconductor Failure Analysis
0.21
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