Enabling cell selection optimization for non-traditional CMOS topologies

The slowdown in improvements due to scaling encourages the exploration of alternative techniques at all design levels. Complementary CMOS logic (CCMOS) has been the dominant digital logic style for several decades. Pass Transistor Logic (PTL) has been studied recently as a low-power alternative to CCMOS but presents challenges to current EDA tools due to strong coupling between inputs and outputs. Thus, circuits that include PTL gates have to be manually designed, limiting their use to regular structures, such as adders and multipliers. Cell selection, or gate sizing, is a crucial optimization step applied to all designs to meet goals for timing and power, but despite the rich literature, only CCMOS gates have so far been considered. In this paper, we present a methodology to accurately model non-traditional CMOS topologies, enabling a broader scope for cell selection and hence more optimization potential. Using our accurate models, we demonstrate reductions of 7% in Critical Path (CP) delay and more than 10% in average power consumption for a representative circuit in a 12 nm FinFET technology.