Information Flow Tracking for Hardware Trojan Detection: a Feasibility Study

While outsourcing hardware designs using FPGA (Field Program-mabIe Gate Array) enables cost optimization in manufacturing, hardware-Trojan insertion during the design process becomes a potential threat to various industrial fields that leverage FPGA boards. In this paper, we propose a system that applies IFT (Information Flow Tracking) to detect hardware Trojans inserted into a DUT (hardware Design Under Test) written in HDL (Hardware Description Language). Unlike existing 1FT techniques for DUTs, our implementation of 1FT tracks the information flow of multiple variables (e.g., registers and wires in Verilog) in simulation. This allows flexible assertion policies used for testing, which can be written like a set of specified variables should not flow to an external channel. By checking if a DUT violates any given policies in simulation, our system detects a hardware Trojan with extracting a statement in HDL and its condition for execution related to the Trojan. These are useful to understand the location of the Trojan and its trigger condition. With an evalution using hardware designs of RS232 (Recommended Standard 232) and AES (Advanced Encryption Standard), we show feasibility of our system for hardware-trojan detection.