A 2.5-12.3 Gb/s continuous-rate referenceless CDR with counter-based unlimited frequency detection

This paper presents a referenceless half-rate clock and data recovery (CDR) circuit that employs a counter-based frequency detector with unlimited frequency acquisition capability. For frequency acquisition, the proposed frequency detector only requires the modified output of the conventional half-rate bang-bang phase detector (BBPD). Regulating the gain of the frequency locked loop (FLL) according to the frequency deviation effectively reduces the overall lock time and minimizes the variation of lock time under different conditions. The simulation results showed that the proposed CDR operates at a wide range of input data rates from 2.5 to 12.3 Gb/s. The power consumption is 3.66 mW at 2.5 Gb/s and 13.44 mW at 12.3 Gb/s. This work is designed using 65 nm process.