Enhancing Embedded Super-Resolution Accelerators: Techniques for Hardware Performance Improvement

Super-resolution (SR) generative models have been widely adopted to enhance the visual quality from low-quality content to high-quality display in many regions, such as disease diagnosis, satellite imagery, and surveillance systems. However, the hardware performance of the SR algorithm on embedded devices suffers from the memory wall and computation complexity due to the inherent characteristic super-resolution method. The abundant external memory access (EMA) requires huge memory bandwidth for image transferring and induces large power consumption for the SR deployed on edge devices. Researchers have proposed several SR accelerators with various novel enhancement techniques to overcome the above drawbacks. In this work, we provide the development of SR accelerators and analyze the trends of techniques for future work of SR accelerators. Moreover, we conclude the research status of the SR hardware and the potential development of future direction.