TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering

Process variability effects and subtle defect mechanisms in deeply scaled analog/mixed-signal/RF (AMS) silicon technologies combine in malicious ways to increase DPPMs of mixed-signal Systems-on-Chips (SoCs). This has driven the need to increase defect coverage while minimizing testing costs. However, testing embedded AMS components in mixed-signal SoCs has always been a challenge due to test access limitations and requirement for labeled data. In this work, we focus on eliminating the requirement for labeled data. As such, rather than measuring the specification values of embedded AMS components, it is more expedient to devise tests using on- chip resources along with low cost mechanisms for identifying outlier behaviors in measured data to identify devices with parametric and catastrophic defects. To resolve this, what is needed are : (a) a test generation methodology that separates outlier from inlier device behaviors making them easily detectable and (b) a response analysis approach that can draw boundaries between multi-dimensional "good" and "outlier" behaviors with such computational ease that it can be invoked in each test generation iteration to quantify the quality of the test being considered. In this context, a novel test stimulus generation approach using clustering of test data in hyperdimensional spaces is developed that maximizes the similarities of inlier devices in the hyperdimensional space thereby allowing outlier devices to be identified easily by their corresponding hypervector representations from their dissimilarity with hypervectors of inlier devices. Such an approach overcomes the major drawback of prior approaches by eliminating the requirement for labeled data. For decision-making, a one-class hyperdimensional classifier that relies on a single cluster boundary (as opposed to complex boundaries in nonlinear spaces), is used to separate "good" vs. "bad" devices. The classifier is computationally efficient, outperforms existing techniques for defect coverage, and drives the search for the optimal test stimulus. Simulation results on test circuits prove the benefits of the proposed approach over prior testing methods.