A Cell-aware Transistor State Stress Model and its Application for Quality Measurement

Stress testing becomes more and more important to excite latent defects and reduce the infant mortality of manufactured ICs. Since no specific stress model exists in the DFT flow, toggle, IDDQ or random tests are typically used to create activity in the design and thus induce stress on the transistors. However, these kinds of tests are not accurate enough since they are mostly generated on the logical gate-level.This paper introduces a Cell-aware Transistor State Stress Model (TSSM) and a methodology to create a stress view for cell libraries as well as an application flow to assess the quality of the stress test patterns. During this flow, the TSSM can be dynamically configured and adapted to technology needs. This new flow uses this cell-aware stress view during simulation to provide a stress coverage of the test set. Experiments show the quality of different test sets and their ability to adapt to different model configurations.