Defect Analysis for FeFETs using a Compact Model

Ferroelectric field-effect transistors (FeFETs) are a promising emerging non-volatile memory, but the impact of manufacturing imperfections on these devices has yet to be studied comprehensively. We extend a previous FeFET compact model to combine the Preisach ferroelectric capacitor model with the BSIM-SOI MOSFET model. We calibrate this new compact model with data from a technology CAD (TCAD) model that is calibrated against a fabricated metal-ferroelectric-metal capacitor. We analyze polarization defects in the ferroelectric layer using this compact model. We address two classes of defects and map them to stuck-at-fault models, referred to as neutral faults (SAP<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup>), and stuck-at-plus and stuck-at-minus (SAP<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and SAP<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup>) faults. This framework obviates the need for computationally expensive TCAD simulations for each defect scenario.