Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States

As the architectural complexity of processors increases dramatically, rigorous functional verification remains essential to ensure performance and immunity from design bugs. A pivotal yet challenging aspect of functional verification is the generation of test instruction streams that are not only highly effective in coverage but also compact enough to significantly reduce verification time. In this paper, we introduce DIG, a novel Dynamic Instruction Generator that leverages processor runtime architectural states through an instruction set simulator. In essence, DIG accesses processor runtime information to produce instruction streams with valid semantics, effectively avoiding illegal memory accesses and infinite loops. The quality of these instruction streams is further enhanced by incorporating both intra-instruction and inter-instruction test knowledge. The effectiveness of DIG is demonstrated through a case study involving Western Digital’s open-source RISC-V core, VeeR EH2. Our experimental results indicate that DIG reduces the number of test instructions by as much as 62.50% and 86.11%, compared to the state-of-the-art random instruction generators, RISC-V DV and RISC-V Torture, respectively, while simultaneously achieving superior functional coverage.