An Integrator Time-Constant Calibration Scheme with Modified Voltage to Digital Converter

This paper presents a time-constant calibration technique with a modified differential 10-bit voltage-to-digital converter. The VDC utilizes a counting-based approach and includes an automatic offset calibration comparator. The comparator performs calibration by controlling the number of compensating MOS transistors connected to the primary input pair. It ensures that the VDC avoids digital code conversion errors caused by MOS mismatch in the comparator. The measured linearity of the VDC is evaluated by linear regression with an R-squared value of 0.9993. Also, the simulation of the time-constant calibration scheme shows the correct calibration result, which indicates the proposed scheme can gain a time-constant error of around 1% from the initial error of ±20%.