One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection

Memory technologies for in-memory computing (IMC) based neural network (NN) operations in edge devices face two primary challenges. First, these technologies often exhibit an excessive average power due to the high currents in the memory’s low and high resistance state (LRS and HRS). Second, their vulnerability to tampering compromises device reliability in security-sensitive Internet of Things (IoT) applications. To tackle these challenges, we propose the use of one-time programmable memory (OTPM) for IMC-based thermal attack-secured and ultra-low powered NN accelerator with write disablement to prevent re-programming/tampering. In this article, first, we show that HRS for OTP memory is exceptionally high (~190 M<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>), but the higher current in LRS (~100 mA) presents a challenge of high average power. We address this challenge by introducing a select transistor gate voltage biasing scheme with the 1T-1OTPM bit cell to reduce LRS current significantly while still trading off the excessive HRS/LRS ratio of 1.5 M to about 1 k. This reduces average power by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 1000\times $ </tex-math></inline-formula> without degrading CIFAR-10 classification performance. Second, we evaluate the impact of OTPM size scaling on HRS and LRS distributions. Though scaling reduces HRS current, we show that moderately scaled 10F<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10$ </tex-math></inline-formula>F OTPM bit cells produce the lowest maximum current in HRS compared to the more aggressively scaled 1F<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 1$ </tex-math></inline-formula>F, which suffers from significant process-induced variability. Third, we show the robustness to temperature, which enables security from thermal attacks.

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Publication Details

Journal
IEEE Journal of the Electron Devices Society
Published
2024-11-29
DOI
https://doi.org/10.1109/jeds.2024.3508759
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.21

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article

One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection

Vivek Saraswat, Ankit Bende, Ajay Kumar Singh, Shubham Patil et al.
1 citations
IEEE Journal of the Electron Devices Society
Advanced Memory and Neural Computing
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article

One-Time Programmable Memory for Ultra-Low Power ANN Inference Accelerator With Security Against Thermal Fault Injection

Vivek Saraswat, Ankit Bende, Ajay Kumar Singh, Shubham Patil, Shreyas Deshmukh, Veeresh Deshpande, Anmol Biswas, Udayan Ganguly, Abhishek Kadam, Diti Sanghai
article en
1 citations

Abstract

Memory technologies for in-memory computing (IMC) based neural network (NN) operations in edge devices face two primary challenges. First, these technologies often exhibit an excessive average power due to the high currents in the memory’s low and high resistance state (LRS and HRS). Second, their vulnerability to tampering compromises device reliability in security-sensitive Internet of Things (IoT) applications. To tackle these challenges, we propose the use of one-time programmable memory (OTPM) for IMC-based thermal attack-secured and ultra-low powered NN accelerator with write disablement to prevent re-programming/tampering. In this article, first, we show that HRS for OTP memory is exceptionally high (~190 M<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>), but the higher current in LRS (~100 mA) presents a challenge of high average power. We address this challenge by introducing a select transistor gate voltage biasing scheme with the 1T-1OTPM bit cell to reduce LRS current significantly while still trading off the excessive HRS/LRS ratio of 1.5 M to about 1 k. This reduces average power by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 1000\times $ </tex-math></inline-formula> without degrading CIFAR-10 classification performance. Second, we evaluate the impact of OTPM size scaling on HRS and LRS distributions. Though scaling reduces HRS current, we show that moderately scaled 10F<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10$ </tex-math></inline-formula>F OTPM bit cells produce the lowest maximum current in HRS compared to the more aggressively scaled 1F<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 1$ </tex-math></inline-formula>F, which suffers from significant process-induced variability. Third, we show the robustness to temperature, which enables security from thermal attacks.

IEEE Journal of the Electron Devices SocietyVol. 13
Indian Institute of Technology Bombay (IN)
Ministry of Electronics and Information technology
Climate action
Openalex Percentile: Top 46%
Advanced Memory and Neural Computing
0.21
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