Efficient adders for nano computing: an approach using QCA

Abstract This research paper presents a detailed evaluation of Quantum-dot Cellular Automata (QCA) digital adder designs utilizing advanced analytical tools, specifically QCADesigner, QCAPro, and QCADesigner-E. The study introduces novel adder designs that significantly enhance cell efficiency, reduce latency, and optimize cost. The study underscores the benefits of using coplanar crossovers to reduce fabrication complexity and avoid additional cell layers, which helps maintain high polarization levels and operational efficiency. The proposed full adder, built using a three-input XOR gate, shows a significant 88% reduction in QCA-specific cost (QSC) and a 0.5 clock cycle reduction in latency compared to the best-optimized existing designs. This improvement is achieved by integrating a single majority gate and MMV gate, removing the need for inverters and consuming 144.2 meV of energy. This design offers a major enhancement over previous designs, which lack such thorough evaluations. Additionally, the proposed ripple carry adder uses 40 fewer cells, achieves a 0.75 clock cycle reduction in latency over the best available design, provides an 81% improvement in QSC, and demonstrates a fully scalable and reliable circuit suitable for nanocomputing applications. Furthermore, the study introduces a single-bit carry look-ahead adder based on half-adder instantiation, with the proposed four-bit carry look-ahead adder achieving a 14% improvement in QCA-specific cost, highlighting its innovative features and practical advantages for advanced QCA circuits.