A 24‐ to 28‐GHz 4×1 MIMO Transmitter/Receiver for 5G Phased‐Array Applications With High Amplitude and Phase Control

ABSTRACT This paper introduces a 4‐channel 24‐ to 28‐GHz RF front‐end MIMO system designed for 5G applications. The transmitter (Tx) and receiver (Rx) chips are fabricated using 130‐nm SiGe BiCMOS technology. The chips contain a 6‐bit phase shifter (PS), 1‐bit attenuator (ATT), 3‐bit variable gain amplifier (VGA), serial peripheral interface (SPI), Wilkinson combiner, power amplifier (PA), and low noise amplifier (LNA). The designed vector‐sum PS, employing a current DAC for semi‐digitization, achieves a 6‐bit phase resolution with minimal root‐mean‐square (RMS) phase error. This design choice allows for the high bit control of the current DAC within a compact chip area. Four‐bit amplitude control is obtained with VGA and ATT. The VGA provides 8‐dB amplitude range while ATT enlarges overall amplitude control with additional 8 dB. L‐R‐L phase compensation technique is utilized to reduce the phase error that arises from ATT. The sub‐blocks are designed to operate with low DC power such that the DC power consumption of overall RX and TX is 50 and 97 mW, respectively. The measurement results of a single‐channel indicate a gain of 15.5‐dB and −25‐dBm IP1dB for the RX chip and 26.5‐dB and 10‐dBm OP1dB for the TX chip while each chip occupies 0.83 mm . The RX chip exhibits a measured noise figure (NF) of 4.3 dB at 26 GHz. Both Tx and Rx chips achieve 6‐bit phase control and 4‐bit amplitude control with low RMS phase error of 2.6° and gain error of 0.3 dB. Low RMS gain and phase errors over a wide bandwidth are attributed to the high precision DAC employed in the control of VGA and PS. Both chips are flip‐chip packaged and undergo upconversion/downconversion via external mixers on a printed circuit board (PCB). System‐level tests with 64‐quadrature amplitude modulation (QAM) show an error vector magnitude (EVM) of 2.72% at 27 GHz for RX and 5.02% at 24 GHz for TX, with a 50‐MBaud modulated signal applied at a data rate of 300 MBps.

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Publication Details

Journal
International Journal of Circuit Theory and Applications
Published
2024-11-27
DOI
https://doi.org/10.1002/cta.4383
Primary Topic
Advanced MIMO Systems Optimization
Type
article
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article

A 24‐ to 28‐GHz 4×1 MIMO Transmitter/Receiver for 5G Phased‐Array Applications With High Amplitude and Phase Control

Ali Bahadir Ozdol, Abdurrahman Burak, Tahsin Alper Özkan, Berke Gungor et al.
International Journal of Circuit Theory and Applications
Advanced MIMO Systems Optimization
article

A 24‐ to 28‐GHz 4×1 MIMO Transmitter/Receiver for 5G Phased‐Array Applications With High Amplitude and Phase Control

Ali Bahadir Ozdol, Abdurrahman Burak, Tahsin Alper Özkan, Berke Gungor, Hamza Kandiş, Yaşar Gürbüz, İlker Kalyoncu, Serafettin Serhan Ozboz
article en

Abstract

ABSTRACT This paper introduces a 4‐channel 24‐ to 28‐GHz RF front‐end MIMO system designed for 5G applications. The transmitter (Tx) and receiver (Rx) chips are fabricated using 130‐nm SiGe BiCMOS technology. The chips contain a 6‐bit phase shifter (PS), 1‐bit attenuator (ATT), 3‐bit variable gain amplifier (VGA), serial peripheral interface (SPI), Wilkinson combiner, power amplifier (PA), and low noise amplifier (LNA). The designed vector‐sum PS, employing a current DAC for semi‐digitization, achieves a 6‐bit phase resolution with minimal root‐mean‐square (RMS) phase error. This design choice allows for the high bit control of the current DAC within a compact chip area. Four‐bit amplitude control is obtained with VGA and ATT. The VGA provides 8‐dB amplitude range while ATT enlarges overall amplitude control with additional 8 dB. L‐R‐L phase compensation technique is utilized to reduce the phase error that arises from ATT. The sub‐blocks are designed to operate with low DC power such that the DC power consumption of overall RX and TX is 50 and 97 mW, respectively. The measurement results of a single‐channel indicate a gain of 15.5‐dB and −25‐dBm IP1dB for the RX chip and 26.5‐dB and 10‐dBm OP1dB for the TX chip while each chip occupies 0.83 mm . The RX chip exhibits a measured noise figure (NF) of 4.3 dB at 26 GHz. Both Tx and Rx chips achieve 6‐bit phase control and 4‐bit amplitude control with low RMS phase error of 2.6° and gain error of 0.3 dB. Low RMS gain and phase errors over a wide bandwidth are attributed to the high precision DAC employed in the control of VGA and PS. Both chips are flip‐chip packaged and undergo upconversion/downconversion via external mixers on a printed circuit board (PCB). System‐level tests with 64‐quadrature amplitude modulation (QAM) show an error vector magnitude (EVM) of 2.72% at 27 GHz for RX and 5.02% at 24 GHz for TX, with a 50‐MBaud modulated signal applied at a data rate of 300 MBps.

International Journal of Circuit Theory and ApplicationsVol. 53(8)
Sabancı Üniversitesi (TR)
Affordable and clean energy
Openalex Percentile: Top 81%
Advanced MIMO Systems Optimization
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