Fault-Tolerant Multitasking System Based on Interleaving of Threads

This paper presents an original approach to error correction in real-time systems. The proposed solution is based on the original multitasking system architecture, which was recently analyzed for energy. The authors have added a structure to correct random errors and distortions at the signal level, increasing reliability. The authors overview their original multitasking, time-predictable, multi-core system. The system has a regular structure with pipelined processing. The threads in each core are interleaved, eliminating the need for complex hazard control mechanisms. Previous works presented issues related to designing a predictable system and scheduling hardware threads with different design goals. The proposed fault detection method is based on scalable redundancy. Replicated processing units correct erroneous register file contents. The replication level can be adapted to current requirements. A mechanism for checking unused registers with “cycle stealing” is proposed with minimal impact on processing continuity. This paper presents the proposed hardware solution implemented in an FPGA device. Experiments using randomly generated errors showed that an additional structure can correct hardware errors. Furthermore, it was shown that the applied solution has a minimal impact on the system performance due to the use of thread interleaving and an error-checking and correction mechanism.