High-Yield Enhancement-Mode GaN <i>p</i>-FET With Etching-Target Layer and High-Selectivity Etching Techniques

This article presents the enhancement-mode (E-mode) GaN p-channel heterojunction field-effect transistors (p-FETs) with p-Al0.05Ga0.95N etching-target layer (ETL). The optimized high-selectivity etching technique achieves an etch rate of approximately 1 nm/min for p-GaN, while also generating a selectivity ratio of 4:1 between p-GaN and p-Al0.05Ga0.95N. High-yield E-mode p-FET with ETL has been obtained as the etching process window was expanded to 10 min. The devices achieved the characteristics of a threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula>) of −1.15 V and a maximum current density (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{{D},\max }$ </tex-math></inline-formula>) of 6.16 mA/mm. Furthermore, the characteristics of multiple devices demonstrate the high consistency and reproducibility of p-FETs’ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}$ </tex-math></inline-formula>, thus providing significant opportunities for developing complementary circuit integration.