A 16-Bit 1.6-kS/s ΔΣ Modulator Based on Folded-Cascode Dynamic Amplifier With Speed Enhancement and PVT-Tracking Techniques

This brief presents a low power high resolution 1-bit quantization-based delta-sigma modulator (DSM). The DSM is designed based on a low-power folded-cascode (LP-FC) current-steering (CS) dynamic amplifier (DA), which has a wide output swing and high gain. A speed enhancement (SE) technique is proposed for LP-FC CS DA to reduce the power consumption further with little gain and noise penalty. Additionally, the proposed PVT-tracking technique (PVTT) compensates the PVT-variation of the output common-mode detection (CMD) circuit of DA with a low dropout regulator (LDO), improving the robustness of DA. The LDO’s output voltage tracks the PVT variations. The prototype DSM is fabricated in 180 nm CMOS technology. The DSM running at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm { S}}$ </tex-math></inline-formula> of 204.8 kHz achieves an SNDR/DR of 94.8/97.3 dB under 1.8 V power supply while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9~\mu $ </tex-math></inline-formula>W, translating into a DR-based Schreier figure of merit (FoMDR) of 176.9 dB.