Analysis and Design of Coarse and Fine Segmented LUT Implementation for FPGA-Based Resource Efficient Wired-Logic DNN Processors

Wired-logic processor architecture is a promising technology for energy-efficient computing. They have achieved several orders of magnitude higher energy efficiency than conventional FPGA-based deep neural network (DNN) processors by eliminating DRAM/BRAM access. The technical challenge of the wired-logic architecture is a huge amount of hardware resources to implement all weights and processing elements as wired-logic circuits. While the non-linear neural network (NNN) was proposed which can save hardware resources by a ternary weight, highly sparse neural network, the area overhead is still large for non-linear function implementation of NNN. Here we developed a coarse- and fine-grained lookup table (LUT) segmentation technique for resource-efficient FPGA-based NNN wired-logic processors. Two techniques are designed and analyzed: (1) an LUT segmentation technique based on coarse and fine granularity, and (2) accuracy optimization through the incorporation of redundant bits. The application of these proposed techniques to state-of-the-art wired-logic processors markedly enhances the scalability achievable with a single FPGA, thereby facilitating the implementation of larger-scale neural networks across various tasks, including CIFAR-10 classification and keyword spotting. The hardware resource requirements for non-linear functions in processing elements decreased by 94.4%, and 95.4%, respectively. Notably, the recognition accuracy for both CIFAR-10 and the keyword spotting task decreased by less than 0.2%, a negligibly small degradation.