Optimized ternary GNRFET-based n-trit full adder with redefined operators

Abstract Multi-valued logic (MVL), specifically three-level logic, has garnered the interest of digital system developers due to its potential benefits. MVL enables larger data representation using the same number of logic bits, resulting in smaller chip area requirements. The utilization of graphene nanoribbon field-effect transistors (GNRFET) in MVL circuit development holds considerable promise, primarily due to the ability to control threshold voltage through graphene nanoribbon (GNR) width manipulation. This study introduces a new design for logic operators, including a 3:1 multiplexer, ternary full-adder (TFA), and 4- and 8-trit ternary ripple carry adders (TRCA) using GNRFETs. This approach uses multiplexers as selection devices and operators as inputs to perform desired operation. We performed comparative analysis of GNRFET-based ternary multiplexers and adders, considering delay, power, and energy as evaluation metrics. The proposed TFA achieves 50.4% improvement in PDP compared to the studied ternary full adders. Moreover, the suggested TRCA scheme enhances PDP by at least 11.65%, compared to studied designs, employing multiplexers to select desired operators. The simulation and analysis were conducted using the HSPICE tool with a 32-nm GNRFET model.