Flip-chip package solder-underfill reliability using finite element analysis

• An FEA model was developed and validated statistically via experimental warpage data. • DOE has identified layer thickness and solder content to significantly affect warpage. • Only layer thickness has a significant effect on the die stress levels. • RSM has identified optimal factors to output minimal warpage and die stress. • A prediction model is developed to guide manufacturing processes. A semiconductor package is responsible to safeguard the die from the external environment that can affect its performance and reliability. A flip-chip package ensures that the assembly, which is capable of high input-output function, maintains its operation and safeguards the interconnection paths particularly the solder ball deformation and fatigue. In this study, a finite element analysis model of the solder-underfill layers of a flip-chip package was developed and validated by statistical comparison of the warpage and stress from experimental data and theoretical calculations of composite deformation and stress. Quarter modeling reduces the computational load while maintaining sufficient detail that allows for efficient use of computational resources. It is then complemented by the design of experiment which systematically varied the parameters to explore the design space and optimize the configuration. Moreover, the method was able to account for nonlinear effects, especially on the impact of solder content on die stress. This provides a more precise control over the thermo-mechanical behavior of the package which would lead to more informed decisions in designing packages. The results have shown desirability of 0.8491 with an optimal layer thickness setting of 0.06 mm and solder content of 18.1 % in consideration of the nonlinear factor effect of solder content on the die stress.