Learning to rank quantum circuits for hardware-optimized performance enhancement

We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>i</mml:mi><mml:mi>b</mml:mi><mml:mi>m</mml:mi><mml:mi>q</mml:mi><mml:mi mathvariant="normal">&amp;#x005F;</mml:mi><mml:mi>g</mml:mi><mml:mi>u</mml:mi><mml:mi>a</mml:mi><mml:mi>d</mml:mi><mml:mi>a</mml:mi><mml:mi>l</mml:mi><mml:mi>u</mml:mi><mml:mi>p</mml:mi><mml:mi>e</mml:mi></mml:math> device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mn>1.8</mml:mn><mml:mo>&amp;#x00D7;</mml:mo></mml:math> reduction in selection error when compared to the baseline approach and a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mn>3.2</mml:mn><mml:mo>&amp;#x00D7;</mml:mo></mml:math> reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

Authors

Publication Details

Journal
Quantum
Published
2024-11-27
DOI
https://doi.org/10.22331/q-2024-11-27-1542
Citations
4
Primary Topic
Quantum Computing Algorithms and Architecture
Type
article
Field-Weighted Citation Impact
1.39
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article

Learning to rank quantum circuits for hardware-optimized performance enhancement

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Quantum
Quantum Computing Algorithms and Architecture
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article

Learning to rank quantum circuits for hardware-optimized performance enhancement

Michael J. Biercuk, Gavin S. Hartnett, Yuval Baum, Michael Hush, Pranav Mundada, Aaron Barbosa
article en
4 citations

Abstract

We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>i</mml:mi><mml:mi>b</mml:mi><mml:mi>m</mml:mi><mml:mi>q</mml:mi><mml:mi mathvariant="normal">&amp;#x005F;</mml:mi><mml:mi>g</mml:mi><mml:mi>u</mml:mi><mml:mi>a</mml:mi><mml:mi>d</mml:mi><mml:mi>a</mml:mi><mml:mi>l</mml:mi><mml:mi>u</mml:mi><mml:mi>p</mml:mi><mml:mi>e</mml:mi></mml:math> device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mn>1.8</mml:mn><mml:mo>&amp;#x00D7;</mml:mo></mml:math> reduction in selection error when compared to the baseline approach and a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mn>3.2</mml:mn><mml:mo>&amp;#x00D7;</mml:mo></mml:math> reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

QuantumVol. 8
Openalex Percentile: Top 15%
Quantum Computing Algorithms and Architecture
1.39
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