Efficient FPGA Implementation of Sine Cosine Algorithm using High Level Synthesis

Sine Cosine Algorithm (SCA) finds the best solution to the optimization problem by the periodicity of sine and cosine trigonometric functions. However, it is computationally intensive and contains many parameters to be determined. Fortunately, there are FPGA platforms that can be used to overcome these limitations by improving latency. Sine and cosine calculation in library functions is very complex and time-consuming. Therefore, this paper proposes a hardware-accelerated CORDIC algorithm to improve the sine cosine trigonometric function that needs to be computed in the SCA algorithm. The proposed algorithm (HSCA) combines the accelerated SCA algorithm and the CORDIC algorithm. HSCA performance is tested by using six test functions run on the FPGA. The experimental results show that HSCA is 3.25 times faster and 33% fewer resource utilizations for solving optimization problems, and runs significantly faster on FPGAs with IP cores than on Soc chips in FPGAs. The performance of the HSCA algorithm is demonstrated by applying it to the TDOA localization problem.