A low-power single ended half-select free 7 T SRAM cell with improved write margin at 32 nm technology node

Abstract A single-ended single port 7T SRAM bit-cell with a process-variation tolerant architecture and half-select resilience at 32 nm CMOS technology node is presented. The proposed 7 T (7TP) SRAM bit-cell integrates a low threshold voltage (LV TH ) feedback cutting transistor along with nominal V TH devices. The reliability of the 7TP cell is presented for process, voltage and temperature (PVT) variations to account for local/global variations incurred during CMOS fabrication. 7TP SRAM bit-cell consistently exhibits 6- σ deviation for static noise margin (SNM), Write Margin (WM) and delay using 1000-point Monte Carlo simulations. The 7TP bit-cell shows improved WM, SNM, power consumption and delay compared to other SRAM cell architectures. The 7TP has the lowest normalized WM-1(WM- 0) of 8.5025%(8.5025%) compared to 17.0150%(46.0875%), 36.5800%(36.5800%), 17.0150%(53.5725%), 53.5450%(14.3650%), 11.8925%(11.8925%) for 7Tn, 7Ti, 7Tj, 8T and 11T SRAM cells respectively. The read-1(read-0) and write-1(write-0) power of the 7TP cell is 887.2 nW(10.09 μW) and 1087 nW(26.6 μW) respectively. The write-1 power of 8 T, 9 T and 10 T cells is 112.2%, 113.70%, and 136.11% of 7TP cell respectively. The proposed cell has the second-best HSNM/RSNM value of 0.269 V at V DD = 0.8 V. The area of the proposed cell is 0.104 sq. μm, the least among other SRAM bit-cells.