A Novel Capacitorless Low-Dropout Regular (LDO) Design for High-Performance System-on-Chip Applications Using 180nm CMOS Process

This paper presents the design and validation of a capacitorless low-dropout regulator (LDO) using 180nm CMOS technology, targeting low power consumption, high power supply rejection ratio (PSRR), and stability for system- on-chip (SoC) applications. Unlike traditional LDOs, which rely on bulky external capacitors, this design eliminates them, reducing size and cost. Key components include a bandgap voltage reference (BGR), startup circuit, error amplifier, and power core, all meticulously designed and simulated. The integrated LDO exhibited excellent performance: a low quiescent current of 78.9μA, near-zero shutdown current, superior line, load regulation, and a PSRR of -61dB at 100kHz. Power gating further reduced idle power consumption. Extensive simulations validated the design’s efficiency and stability, making it suitable for portable, low-power applications. This work addresses conventional LDO limitations and lays the foundation for future capacitorless LDO designs, promoting more compact and efficient power management solutions.