The Low-Complexity Timing Synchronization Circuits for IEEE 802.15.4a/z IR-UWB Systems

This paper presents the design and implementation of a low-complexity timing synchronization circuit for the IEEE 802.15.4a/z IR-UWB wireless communication standard. The circuit structure of a low-complexity correlator for complex ternary values is designed. Moreover, a two-stage synchronization approach is utilized for a more accurate sample alignment. Therefore, a balance between the performance of synchronization and hardware complexity is achieved. The proposed synchronization architecture is designed and implemented based on the Xilinx ZC706 FPGA platform. The experimental results show that the proposed design saves 74% of buffer and 87.4% of multiplier utilization.