Insights Into Threshold Voltage Variability in Negative Capacitance Junctionless Transistor

This work investigates the statistical variability of threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\sigma V_{\mathrm { th}})$ </tex-math></inline-formula> and its sensitivity to critical geometrical parameters in negative capacitance (NC) junctionless (JL) and conventional JL transistors through quantum-corrected TCAD simulations. Threshold voltage variability <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\sigma V_{\mathrm { th}})$ </tex-math></inline-formula> considering the statistical variation is assessed by varying the gate length, film thickness, channel doping, equivalent oxide thickness, and ferroelectric thickness. Results showcase <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\mathrm { th}}$ </tex-math></inline-formula> owing to the process-induced variation in the device parameters can be reduced considerably by integrating the ferroelectric layer in the gate stack of JL devices. Among all the device parameters, variability analysis shows that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\mathrm { th}}$ </tex-math></inline-formula> degrades more against the variation in film, equivalent oxide, and ferroelectric thicknesses. As channel doping is critical to NCJL devices, we showcase that designing the NCJL transistors with moderate channel doping of 1018 cm-3 considerably lowers the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\mathrm { th}}$ </tex-math></inline-formula> against the device parameter variation. This work features the systematic methodology to lower the process-induced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { th}}$ </tex-math></inline-formula> variability in NCJL devices while highlighting the potential significance of moderately doped channels at shorter technology nodes.

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Publication Details

Journal
IEEE Journal of the Electron Devices Society
Published
2024-11-22
DOI
https://doi.org/10.1109/jeds.2024.3505620
Citations
1
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.21
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article

Insights Into Threshold Voltage Variability in Negative Capacitance Junctionless Transistor

S R Ruma, Manish Gupta, Vita Pi‐Ho Hu
1 citations
IEEE Journal of the Electron Devices Society
Advancements in Semiconductor Devices and Circuit Design
0.21
article

Insights Into Threshold Voltage Variability in Negative Capacitance Junctionless Transistor

S R Ruma, Manish Gupta, Vita Pi‐Ho Hu
article en
1 citations

Abstract

This work investigates the statistical variability of threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\sigma V_{\mathrm { th}})$ </tex-math></inline-formula> and its sensitivity to critical geometrical parameters in negative capacitance (NC) junctionless (JL) and conventional JL transistors through quantum-corrected TCAD simulations. Threshold voltage variability <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\sigma V_{\mathrm { th}})$ </tex-math></inline-formula> considering the statistical variation is assessed by varying the gate length, film thickness, channel doping, equivalent oxide thickness, and ferroelectric thickness. Results showcase <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\mathrm { th}}$ </tex-math></inline-formula> owing to the process-induced variation in the device parameters can be reduced considerably by integrating the ferroelectric layer in the gate stack of JL devices. Among all the device parameters, variability analysis shows that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\mathrm { th}}$ </tex-math></inline-formula> degrades more against the variation in film, equivalent oxide, and ferroelectric thicknesses. As channel doping is critical to NCJL devices, we showcase that designing the NCJL transistors with moderate channel doping of 1018 cm-3 considerably lowers the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma V_{\mathrm { th}}$ </tex-math></inline-formula> against the device parameter variation. This work features the systematic methodology to lower the process-induced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { th}}$ </tex-math></inline-formula> variability in NCJL devices while highlighting the potential significance of moderately doped channels at shorter technology nodes.

IEEE Journal of the Electron Devices SocietyVol. 13
National Taiwan University (TW), Birla Institute of Technology and Science, Pilani - Goa Campus (IN), Birla Institute of Technology and Science, Pilani (IN)
Affordable and clean energy
Openalex Percentile: Top 46%
Advancements in Semiconductor Devices and Circuit Design
0.21
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