Assessment of Leakage Current Reduction Techniques for Si-Stacked Nanosheet Transistor at 3-nm Node and Beyond

This study explores how different methods of reducing leakage current affect the performance of Si nanosheet field effect transistors (NS-FETs) at sub-3-nm technology nodes. We examine the impact of punch-through stopper (PTS) and bottom dielectric isolation (BDI) techniques on lattice temperature of the device and stress induced in the channel. We use a new simulation method that combines quantum-mechanically corrected Monte Carlo (MC) simulation and calibrated drift-diffusion. The TCAD model is calibrated with the most recent experimental data available in the literature. At the same node technology, our research revealed an increase by 44 K in lattice temperature due to the BDI scheme compared to the PTS scheme. The study also revealed a decrease by 88% in the channel stress, and a reduction in the ON-current by 18%. The PTS schemes suffer from the short channel effects (SCEs) compared to the BDI structures.