A Low-Power 64Gb/s PAM4 Transmitter in 65nm CMOS

This paper introduces a Pulse Amplitude Modu-lation with 4 levels (PAM4) wireline transmitter capable of operating at data rates up to 64 Gb/<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$s$</tex> using 65 nm CMOS technology. It presents methods to mitigate the need for inductors and includes a serializer divided into three stages: a transmission gate-based CMOS multiplexer (mux), a charge steering mux, and a 4:1 CML mux. This architecture balances speed and power and features a source-series terminated (SST) driver with its high linearity and low power consumption. The proposed PAM4 transmitter alleviates the need for inductive peaking or CML drivers, which are common in literature saving area and power. The proposed PAM4 transmitter is verified against PVT corners, achieves a 1.14 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{PP}$</tex> output swing, a ratio of level mismatch (RLM) of 98.3%., and consumes 60.8mW. It features a 0.7 UI horizontal eye and a power efficiency of 0.95 pJ/bit,