A Saliency-Aware Analog Computing In-memory with SAR-Embedded Detection Achieving 18.5% Power Reduction

Abstract In this paper, we introduce a saliency-aware analog computing in-memory macro to mitigate the trade-off between the accuracy and power consumption of computing in-memory (CIM) by optimizing the analog to digital converter (ADC) resolution according to the importance of input data, also known as saliency. This is realized with minimal hardware overheads using the proposed successive approximation register (SAR)-embedded saliency detection technique (S2DT), which reconfigures the capacitive digital to analog converter of the SAR ADC. Saliency is determined by the magnitude of the multiply and accumulate (MAC) values. In the saliency detector, an S2DT is used to generate a threshold, classifying saliency into three levels based on the MAC magnitude to switch the ADC resolution. The chip is fabricated in TSMC 65nm complementary metal-oxide semiconductor (CMOS) technology, achieving up to 18.5% improvement in power consumption of the ADC compared to CIM without utilizing saliency, demonstrating an accuracy of 74.6% to 83.4% on the CIFAR-10 dataset.