Eye-Diagram Edge Estimation (EEE) Network for Through Silicon via Design in Next-Generation High Bandwidth Memory

In this paper, we propose an eye-diagram edge estimation (EEE) network for fast and accurate eye diagram prediction, which is a novel approach in through silicon via (TSV) design in high bandwidth memory (HBM). As HBM generation is developed, the number of input/outputs (I/Os) and data rate have increased for high bandwidth, causing degradation of signal integrity (SI) in TSV structures. However, SI evaluation takes much time due to time-consuming SI simulations including the eye diagram simulation. Therefore, there is a need for fast eye diagram estimation for TSV structures optimization. The proposed EEE network utilizes only four voltage values at each time step to predict the eye diagram edge. In addition, the EEE network does not require additional time-domain and frequency-domain simulations, enabling a significant reduction in model size and facilitating training with a small dataset and shallow models such as artificial neural network (ANN). As a result, the ANN-based EEE network generated an eye diagram edge with an approximate 1% error in under 1 ms, demonstrating high accuracy and time-efficiency. This novel approach has potential applications in other design scenarios.