Design of Area-Efficient and Low-Power Magnetic Full Adder

Complementary metal oxide semiconductor (CMOS) is an extensively used promising technology for developing integrated circuits, such as memory chips, microprocessors and microcontrollers with high noise immunity. However, deep scaling of CMOS technology ([Formula: see text] [Formula: see text]nm) suffers from various impediments at the device and architectural level, namely high leakage current, increased radiation sensitivity, more die area and dynamic power dissipation. To overcome these limitations of CMOS devices, logic-in-memory (LIM) structures have been developed with spin-based devices like Magnetic Tunnel Junctions (MTJs). MTJs are not affected by external particles and feature zero standby power. The MTJs in magnetic logic circuit and magnetic random-access memory (MRAM) applications are robust against radiation, high speed, low leakage power, nonvolatility and easily compatible with the back end. Existing magnetic full adder (MFA) techniques require augmented circuits for seamless operation. A major drawback in the existing MFA structure is the data loss due to single event upset (SEU) and poor sensitivity of pre-charge sense amplifiers (PCSAs) to input arrival timing. This paper proposes an MTJ-based nonvolatile magnetic full adder (NV-MFA) using 10T logic to address the above issues. The output buffer circuit is designed with a read-write parallel switching (RWPS) writing circuit based on spin orbit torque (SOT). The proposed circuit is more immune to the fault occurrence compared with the existing pass transistor and PCSA-based MFA logic. It leads to reduced power dissipation, die area and delay. Perpendicular anisotropy MTJ (CoFeB/MgO/CoFeB) model is chosen for the MTJ structure. It is suitable for efficient MRAM structure. The transient response is verified on Cadence virtuoso using 45[Formula: see text]nm gpdk CMOS technology. The simulation analysis shows the performance is enhanced with fault-free data output and improved reliability compared with previous MFAs.

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Publication Details

Journal
SPIN
Published
2024-11-21
DOI
https://doi.org/10.1142/s2010324724500231
Citations
2
Primary Topic
Magnetic properties of thin films
Type
article
Field-Weighted Citation Impact
0.68

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article

Design of Area-Efficient and Low-Power Magnetic Full Adder

R. Sreeja, J. Kamala, K. Sahaana
2 citations
SPIN
Magnetic properties of thin films
0.68
article

Design of Area-Efficient and Low-Power Magnetic Full Adder

R. Sreeja, J. Kamala, K. Sahaana
article en
2 citations

Abstract

Complementary metal oxide semiconductor (CMOS) is an extensively used promising technology for developing integrated circuits, such as memory chips, microprocessors and microcontrollers with high noise immunity. However, deep scaling of CMOS technology ([Formula: see text] [Formula: see text]nm) suffers from various impediments at the device and architectural level, namely high leakage current, increased radiation sensitivity, more die area and dynamic power dissipation. To overcome these limitations of CMOS devices, logic-in-memory (LIM) structures have been developed with spin-based devices like Magnetic Tunnel Junctions (MTJs). MTJs are not affected by external particles and feature zero standby power. The MTJs in magnetic logic circuit and magnetic random-access memory (MRAM) applications are robust against radiation, high speed, low leakage power, nonvolatility and easily compatible with the back end. Existing magnetic full adder (MFA) techniques require augmented circuits for seamless operation. A major drawback in the existing MFA structure is the data loss due to single event upset (SEU) and poor sensitivity of pre-charge sense amplifiers (PCSAs) to input arrival timing. This paper proposes an MTJ-based nonvolatile magnetic full adder (NV-MFA) using 10T logic to address the above issues. The output buffer circuit is designed with a read-write parallel switching (RWPS) writing circuit based on spin orbit torque (SOT). The proposed circuit is more immune to the fault occurrence compared with the existing pass transistor and PCSA-based MFA logic. It leads to reduced power dissipation, die area and delay. Perpendicular anisotropy MTJ (CoFeB/MgO/CoFeB) model is chosen for the MTJ structure. It is suitable for efficient MRAM structure. The transient response is verified on Cadence virtuoso using 45[Formula: see text]nm gpdk CMOS technology. The simulation analysis shows the performance is enhanced with fault-free data output and improved reliability compared with previous MFAs.

SPINVol. 15(01)
Anna University, Chennai (IN)
Anna University
Affordable and clean energy
Openalex Percentile: Top 30%
Magnetic properties of thin films
0.68
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