Design of a Low-Power 8+T SRAM for In-Memory Computing Operations

SRAM-based in-memory computing is one of the technologies addressing the von Neumann architecture's bottleneck.Designing efficient SRAM bit cells is crucial for the effective implementation of SRAM-based in-memory computing.In this paper, we propose a novel 8+T SRAM design for low-power differential sensing, aimed at enhancing circuit performance and reducing power consumption.The proposed 8+T SRAM bit cells enable parallel execution of logic operations, including ripple-carry adders and content-addressable memory (CAM) functions.Our design reduces power consumption by 21.25% compared to previous 8+T SRAM-based ripple-carry adders, though it introduces a 10.98% increase in propagation delay.Additionally, the power-delay product (PDP) for the adder is lowered by 12.63%.For CAM, our approach decreases energy consumption by 7.06% compared to previous designs.The feasibility of the proposed circuit is validated through SPECTRE simulations with TSMC 65nm CMOS process.